Crystallographic Silicon-etching for Ultra-High AspectRatio FinFET”, Trans

The challenge of moving towards ultimate CMOS scaling-limit depends on the ability to contain short-channel effects (SCE). The double- or triple-gate FinFET is considered the best candidate to suceed planar bulk devices for the 22 nm node and beyond in various applications, such as digital logic [1], SRAM [2], DRAM [1] and Flash memory [3]. FinFETs offer better gate control of the channel which reduces SCE. A small width of the etched fin is necessary for good SCE control, and at the same time high quality of the etched surfaces is needed to reduce surface scattering. Additionally, with the channel positioned vertically to the wafer surface, tall silicon fins can significantly increase the driving current of the FinFET. Anisotropic properties of silicon etching usin